This application claims the priority benefit of Korean Patent Application No. 2000-69982, filed on Nov. 23, 2000, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to the field of an integrated circuit device, and more particularly to a voltage boosting circuit for an integrated circuit device.
Nonvolatile semiconductor memory devices for integrated circuit devices are expected to experience a sharp increase in market demand. That is because such devices (and especially flash memory devices) will be used in portable devices such as cellular phones and personal digital assistants (PDAs).
Portable devices are limited by their batteries. To reduce power consumption, portable devices strive to operate on lower power supply voltages. This extends their usage time from a single battery, and results in these devices becoming lighter.
While the available power supply voltages are becoming lower, the integrated circuit devices compensate for this by generating higher voltages internally. This is accomplished by boosting circuits, which use a boosting mechanism to generate a high voltage (hereinafter refer to as boosted voltage).
One of the challenges is to maintain the boosted voltage uniform, even though the level of the external power supply voltage changes. If the boosted voltage is instead permitted to fluctuate, the applied voltage to MOS transistors also fluctuates. This causes serious problems in operating the integrated circuit device. For example, there may be a malfunction by applying an excessive high voltage. That is because a voltage higher than a breakdown voltage is applied to a p-n junction in the integrated circuit device. Further, there may also be a destruction of an insulation film in the MOS transistors, which would suddenly increase power consumption.
Referring now to FIG. 1, a method has been developed to reduce the fluctuation of a boosted voltage, when a power supply voltage is varied. The method is proposed in the paper titled xe2x80x9cA 2.7V Only 8 Mb""16 NOR Flash Memoryxe2x80x9d (IEEE 1996 Symposium On VLSI Circuits Digest of Technical Papers, pp. 172-173). The voltage boosting circuit of the proposed paper is reproduced in FIG. 1.
Referring to FIG. 1, the essence of the method is to control the number of capacitors used in the boosting mechanism. A conventional voltage boosting circuit is constructed of a booster 10 and a control logic 12. The booster 10 includes two inverters 20 and 24, two capacitors 22 and 26, and a PMOS transistor 28, connected as shown in FIG. 1.
The booster 10 generates a boosted voltage VPP higher than a power supply voltage VCC, in response to a low-to-high transition of a control signal. According to a control signal Vcdet, the control logic 12 determines the number of capacitors to be used in the booster 10 by an alternative selection of inverters 20 and 24 in the booster 10. A voltage level of the control signal Vcdet can be determined by a voltage divider (not shown), for dividing the boosted voltage VPP.
If the voltage level of the control signal Vcdet rises in accordance with an increase of the boosted voltage VPP, the control logic 12 disables one of inverters 20 and 24 used in the booster 10. Namely, the booster 10 operates by using one capacitor, and therefore the VPP is decreased by about a half. If the VPP becomes low, the control logic 12 enables a disabled inverter. The booster 10 then operates by using the two capacitors 22, 26, and therefore the VPP becomes high again.
FIG. 2 is a graph showing a relation of fluctuation of the power supply voltage and variation of boosted voltage in a conventional voltage boosting circuit. If the power supply voltage is positioned between VCC1 and VCC2, the control logic 12 is designed to use both capacitors 22 and 26 of the booster 10. In this case, the boosted voltage VPP from the booster 10 is positioned between VPP1 and VPP2 by a boosting operation using a couple of capacitors. If the power supply voltage is leveled between VCC2 and VCC3, the control logic 12 is designed to use one of capacitors 22 and 26 of the booster 10. In this case, the boosted voltage VPP is positioned between VPP2 and VPP1 by a boosting operation using one capacitor.
FIG. 2 is a graph VPP(10), which shows a boosted voltage VPP having wide variations depending on variations in the power supply voltage VCC. It means that an integrated circuit device (which receives VPP as its power supply) has an unstable operation.
Therefore, to ensure a stable operation, there exists a need for a voltage boosting circuit that fluctuates very little due to variations in the power supply voltage.
The object of the present invention is to provide a voltage boosting circuit for an integrated circuit which outputs a boosted voltage with reduced fluctuations as a result of variations in the power supply voltage.
According to an aspect of the present invention, the voltage boosting circuit for an integrated circuit includes a booster and a voltage clamp circuit. The booster generates a boosted voltage higher than the supply voltage in response to a boosting control signal. The voltage clamp circuit includes a voltage detector, a pulse generator, and a discharge circuit. The voltage detector generates, in response to the boosting control signal, a detected voltage signal representing an attribute of the boosted voltage. The pulse generator generates a pulse signal responsive to the detected voltage signal. And the discharge circuit discharges the boosted voltage during an activation period of the pulse signal. This largely stabilizes the output voltage of the booster.